1. Field of the Invention
The present invention relates to a data processing circuit and a signal processing system, and, in particular, to a data processing circuit and a signal processing system in which, in a multiplexing/demultiplexing circuit of a high-speed optical communication or such, when parallel data signals are transmitted at a high speed, phase adjustment to an internal operation clock signal provided of a circuit receiving the parallel data signals can be carried out accurately.
2. Description of the Related Art
For example, in an optical communication system carrying out optical transmission at a very high data transfer rate such as 40 Gb/s, signal transmission of parallel data signals of 622 Mb/s×64 channels, 2.5 Gb/s×16 channels or such are carried out between respective circuits inside of a transmission apparatus. In order to achieve precise signal transmission without data error in transmission of such parallel data signals, it is necessary to establish phase synchronization between a transmission side circuit and a reception side circuit for each signal. However, a transmission length between the circuits, a delay time occurring inside of an IC or such is not fixed, and thus, a fluctuation may occur therein. Thereby, a phase difference may occur among the signals transmitted in parallel, which may result in a signal error. In particular, as the signal transmission rate increases, influence of such a delay time increases accordingly. In fact, in a case of a very high transmission rate such as 40 Gb/s, fluctuation in such a delay time, which could have been ignored until then, will directly result in a signal error. Therefore, a measure enabling accurate phase adjustment is demanded.
Japanese Laid-open Patent Application No. 10-107786 discloses a method in which a separation of phase between an input side frame and an output side frame is monitored, and, a timing of a frame signal is determined in such a manner that the phase separation therebetween may have a proper amount. However, according to this method, an input signal should be once held by a parallel buffer. For this purpose, a large size of the parallel buffer is required, and also, a signal delay necessarily occurs since a sufficiently large separation should be provided between the input and the output in this method.